1. Technical Field
This disclosure relates generally to image sensors, and in particular, but not exclusively to complementary metal-oxide semiconductor (“CMOS”) image sensors.
2. Background Art
Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as, medical, automobile and other applications. The technology used to manufacture image sensors, and in particular complementary metal-oxide semiconductor (“CMOS”) image sensor, has continued to advance at a great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of these image sensors.
FIG. 1A is a circuit diagram illustrating pixel circuitry of two four-transistor (“4T”) pixel cells Pa and Pb (collectively pixel cells 100) within a conventional image sensor array. Pixel cells Pa and Pb are arranged in two rows and one column and time share a single readout line. Each pixel 100 includes photodiode 101, transfer transistor 102, reset transistor 103, source-follower transistor 104 and row select transistor 105.
During operation, transfer transistor 102 receives transfer signal TX which transfers the charge accumulated in photodiode 101 to floating diffusion node 106. Reset transistor 103 is coupled between power rail VDD and floating diffusion node 106 to reset the pixel (e.g. discharge or charge floating diffusion node 106 and photodiode 101 to a preset voltage) under the control of reset signals RST. Floating diffusion node 106 is coupled to the gate terminal of source-follower transistor 104. Source-follower transistor 104 is coupled between power rail VDD and row select transistor 105. Source-follower transistor 104 operates as a source-follower, providing a high impedance connect to floating diffusion node 106. Row select transistor 105 selectively couples the output of pixel cell 100 to readout column line or bit line under the control of signal RS.
In normal operation, photodiode 101 and floating diffusion node 106 are reset during a reset phase by temporarily asserting reset signal RST and transfer signal TX. After the reset phase, the integration phase is commenced by de-asserting transfer signal TX and reset signal RST and permitting incident light to charge photodiode 101. The voltage or charge on photodiode 101 is indicative of the intensity of light incident of photodiode 101 during the integration phase. The readout phase is commenced before the end of the integration phase by asserting reset signal RST to reset floating diffusion node 106 to reset voltage RST. RST approximately equals power rail VDD minus the threshold voltage of reset transistor 103. After floating diffusion node 106 has been reset, row select signal RS and a sample signal are asserted, which couples floating diffusion node 106 to a sample and hold circuit (not shown). After the reset voltage is sampled, the sample signal is de-asserted. The end of the integration phase occurs after the de-assertion of the sample signal. Transfer signal TX is then asserted to couple photodiode 101 to floating diffusion node 106 and the gate terminal of source-follower transistor 104. As the accumulated electrons on photodiode 101 is transferred to floating diffusion node 106, the voltage at floating diffusion node 106 decrease since electrons are negative charge carriers. After charge transfer is complete, transfer signal TX is de-asserted. After transfer signal TX is de-asserted, sample signal RS is asserted and the voltage at floating diffusion node 106 is sampled.
When reset signal RST is asserted during the reset phase and the beginning of the readout phase, the channel region of reset transistor 103 is inverted and electrons are injected into the channel. When reset signal RST is de-asserted, some charges will be injected to the terminal coupled to power rail VDD and other charges will be injected to the terminal coupled to floating diffusion node 106.
The voltage potential well at floating diffusion node 106 after a pixel is reset strongly relates to the occurrence of image lag at a high signal level. Consequently, a decrease in the potential well of floating diffusion node 106 would decrease the voltage swing and the conversion gain of the pixel cell (and therefore the image sensor). The post-reset potential well at floating diffusion nodes tends to become shallower as successively smaller-sized pixels are developed. These shallow potential well characteristics pose a serious limitation on improving image sensor performance.